1. Field of the Invention
The present invention relates to a circuit, a control system, an IC (Integrated Circuit), a transmitting and receiving apparatus, a control method, and a program that reduce a phase error and simultaneously suppress a high-frequency jitter component and a low-frequency wander component.
2. Description of the Related Art
Conventionally, there is widely used a PLL (Phase Locked Loop) circuit which reproduces a clock of an SDH (Synchronous Digital Hierarchy) signal from an OTN (Optical Transport Network) signal.
For example, Japanese Patent Application Laid-Open No. 2000-278126 proposes a technique to provide a PLL circuit. In this document, the PLL circuit includes two kinds of phase comparators. The higher accuracy phase comparator is selected depending on magnitude of a phase difference between an input signal and an oscillator output and the output of the higher accuracy phase comparator is led to a loop filter to obtain high frequency accuracy and phase accuracy. Also, the input signal or a signal obtained by dividing the input signal is used as a signal source of a sampling frequency of the loop filter, and the high-speed response is obtained over a wide frequency band by causing a characteristic frequency of the loop filter to follow a frequency increase or decrease of the input signal. Also, using a numerical control oscillator, continuous and high-speed frequency change is enabled in a wide input frequency range and a good transient response is obtained. Further, when a phase difference is remarkably large between the input signal and the oscillator output, namely, when the PLL circuit is unlocked, a detection value of an input signal frequency is set at an output frequency of an oscillator to improve a follow-up speed at the large frequency change of the input signal, and thereby the high accuracy and high-speed response are obtained with a simple configuration over a wide input frequency range.
However, there are the following problems in the PLL circuit proposed in Japanese Patent Application Laid-Open No. 2000-278126.
When the SDH signal clock is reproduced from the OTN signal, both a high-frequency jitter component and a low-frequency wander component are generated due to asynchronous stuff multiplex. Two problems arise for a high-frequency jitter suppression circuit and a low-frequency wander suppression circuit.
The first problem is cost increase. In order to suppress the low-frequency wander component generated when an SDH signal clock is reproduced from the OTN signal, it is necessary that a phase noise cutoff frequency of the PLL circuit be set in the range of about 0.1 Hz to about 1 Hz. In this case, because a phase error is increased, it is necessary that the suppression of the low-frequency wander component be realized by a complete integral type PLL circuit having a large circuit scale as shown in FIG. 1, which leads to the cost increase. When the cutoff frequency is set at a low frequency, a pull-out/lock range, which is a dynamic range and is different from a hold-in/pull-in range of a static range, is narrowed so that function of suppressing the high-frequency jitter component decreases.
That is, when the high-frequency jitter component exceeding the pull-out/lock range of PLL is inputted, although the high-frequency jitter component is suppressed, the jitter component that is not controlled in the pull-out/lock range is superposed every PLL control cycle (natural angular frequency), which generates the new jitter and wander components.
Specifically, when the cutoff frequency is set in the range of about 0.08 Hz to 0.1 Hz, a direct-current loop gain is about 0.5. For example, when a high-frequency jitter component of 1000 ns is inputted, an amount of frequency fluctuation is computed at 0.5 ppm from a phase fluctuation angle (φ=Δω/direct-current loop gain). This means that a pull-out/lock range needs to be 0.5 ppm or more in theory. However, when the cutoff frequency is set in the range of about 0.08 Hz to 0.1 Hz, it is actually difficult to keep the pull-out/lock range 0.5 ppm or more.
More specifically, the pull-out/lock range (ΔωpL) can be computed from the direct-current loop gain and a phase comparison frequency. At this point, because one frame period of 328 kHz of an OTU2 signal becomes the phase comparison frequency, the frequency-converted pull-out/lock range is computed as (0.5/2π)/328 kHz=0.2426 ppm from ΔωpL=Ko=0.5. Therefore, a design condition when a high-frequency jitter component of 1000 ns is inputted, namely a condition that the pull-out/lock range is not lower than 0.5 ppm, cannot be satisfied.
Accordingly, in theory, it is difficult to suppress both the high-frequency jitter component and the low-frequency wander component simultaneously only by one stage of the complete integral type PLL circuit shown in FIG. 1.
Another problem is superposition of a phase error Ess (Steady State Error). In order to avoid the problem of the cost increase, for example, when the multiple-stage connection is realized by small scale incomplete integral type PLL circuits including high-frequency jitter suppression circuits and low-frequency wander suppression circuits as shown in FIG. 2, although the high-frequency jitter component and the low-frequency wander component can simultaneously be suppressed, the phase error Ess generated in each PLL circuit is superposed at the same time.
The superposition of the phase error Ess can be understood with Formula 1.
                                          Ess            Multiloop                    =                                    Δ              ⁢                                                          ⁢              ω                                      K                              o                ⁢                                                                  ⁢                1                                                    ⁢                                  ⁢                              Ess            Cascade                    =                                                    Δ                ⁢                                                                  ⁢                ω                                            K                                  o                  ⁢                                                                          ⁢                  1                                                      +                          Δω                              K                                  o                  ⁢                                                                          ⁢                  2                                                      +                          Δω                              K                                  o                  ⁢                                                                          ⁢                  3                                                                                        [                  Formula          ⁢                                          ⁢          1                ]            
Accordingly, the phase error increases as the number of multiple-stage connections increases, so that the multiple-stage connection is hardly realized with the conventional incomplete integral type PLL circuit.